## Generated SDC file "c4gx15_qsys_pcie_gen1x1_11_1.out.sdc"

## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.0 Build 206 06/15/2011 Service Pack 1 SJ Full Version"

## DATE    "Tue Jun 28 15:58:52 2011"

##
## DEVICE  "EP4CGX15BF14C6"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {clkin_sys} -period 20.000 -waveform { 0.000 10.000 } [get_ports { clkin_sys }]
create_clock -name {refclk} -period 10.000 -waveform { 0.000 5.000 } [get_ports { refclk }]


#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pma0|clockout} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[1]}] -duty_cycle 50.000 -multiply_by 1 -master_clock {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[1]} [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pma0|clockout}] 
create_generated_clock -name {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0|hiptxclkout} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0|localrefclk}] -duty_cycle 50.000 -multiply_by 1 -master_clock {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pma0|clockout} [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0|hiptxclkout}] 
create_generated_clock -name {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0|hiptxclkout}] -duty_cycle 50.000 -multiply_by 1 -divide_by 2 -master_clock {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0|hiptxclkout} [get_pins {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] 
create_generated_clock -name {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout} -source [get_pins {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -duty_cycle 50.000 -multiply_by 1 -master_clock {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0} [get_pins {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] 
create_generated_clock -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -master_clock {clkin_sys} [get_pins {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] 
create_generated_clock -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 5 -divide_by 2 -master_clock {clkin_sys} [get_pins {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] 
create_generated_clock -name {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|icdrclk} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 25 -divide_by 2 -master_clock {refclk} [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|icdrclk}] 
create_generated_clock -name {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[0]} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 25 -divide_by 2 -master_clock {refclk} [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[0]}] 
create_generated_clock -name {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[1]} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 5 -divide_by 2 -master_clock {refclk} [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[1]}] 
create_generated_clock -name {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[2]} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|inclk[0]}] -duty_cycle 20.000 -multiply_by 5 -divide_by 2 -master_clock {refclk} [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|clk[2]}] 
create_generated_clock -name {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|receive_pma0|clockout} -source [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|icdrclk}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|pll0|auto_generated|pll1|icdrclk} [get_pins {u0|pcie_hard_ip_0|altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|receive_pma0|clockout}] 


#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -setup 0.060 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -hold 0.090 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -setup 0.060 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -hold 0.090 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.080 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.110 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.080 
set_clock_uncertainty -rise_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.110 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -setup 0.060 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -hold 0.090 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -setup 0.060 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}] -hold 0.090 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.080 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.110 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.080 
set_clock_uncertainty -fall_from [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.110 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.160 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.160 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.160 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|pcie_hard_ip_0|pcie_internal_hip|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout}]  0.160 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {reconfig_pll|altpll_component|auto_generated|pll1|clk[1]}]  0.020 


#**************************************************************
# Set Input Delay
#**************************************************************



#**************************************************************
# Set Output Delay
#**************************************************************



#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] 
set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] 
set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] 


#**************************************************************
# Set False Path
#**************************************************************

set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -from [get_ports {pcie_rstn}] 
set_false_path -from [get_ports {user_pb[*]}] 
set_false_path -to [get_ports {L0_led}]
set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}]


#**************************************************************
# Set Multicycle Path
#**************************************************************



#**************************************************************
# Set Maximum Delay
#**************************************************************

set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|receive_pcs0~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|receive_pcs0~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLEDPRIOLOAD }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLEDPRIODISABLE }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLERXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLETXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLERXANALOGRESET }] 20.000
set_max_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLEDPRIORESET }] 20.000


#**************************************************************
# Set Minimum Delay
#**************************************************************

set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|receive_pcs0~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|receive_pcs0~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|transmit_pcs0~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLEDPRIOLOAD }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLEDPRIODISABLE }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLERXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLETXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLERXANALOGRESET }] 0.000
set_min_delay -to [get_ports { q_sys:u0|q_sys_pcie_hard_ip_0:pcie_hard_ip_0|q_sys_pcie_hard_ip_0_altgx_internal:altgx_internal|q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8:q_sys_pcie_hard_ip_0_altgx_internal_alt_c3gxb_i9h8_component|cent_unit0~OBSERVABLEDPRIORESET }] 0.000


#**************************************************************
# Set Input Transition
#**************************************************************

